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9zx21501b idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 15-output differential zbuffer for pcie gen2/3 and qpi 1 datasheet description the ics9zx21501 is a 15 output version of the intel db1900z differential buffer suitable for pcie gen3 or qpi applications. the part is backwards compatible to pcie gen1 and gen2. an adjustable external feedback path allows the user to eliminate trace delays from their design while maintaining low drift for critical qpi applications. in bypass mode, the ics9zx21501 can provide outputs up to 400mhz. key specifications ? cycle-to-cycle jitter: < 50ps ? output-to-output skew: <65ps ? input-to-output delay: user adjustable ? input-to-output delay variation: <50ps ? phase jitter: pcie gen3 < 1ps rms ? phase jitter: qpi 9.6gb/s < 0.2ps rms features/benefits ? external feedback path/ adjustable input-to-output delay ? 9 selectable smbus addresses/ multiple devices can share same smbus segment ? 7 dedicated oe# pins/ hardware control of outputs ? pll or bypass mode/ pll can dejitter incoming clock ? selectable pll bw/ minimizes jitter peaking in downstream pll's ? spread spectrum compatible/tracks spreading input clock for emi reduction ? smbus interface/ unused outputs can be disabled ? 100mhz & 133.33mhz pll mode/ legacy qpi support ? undriven differential outputs in power down mode for maximum power savings functional block diagram recommended application 15 output pcie gen3/qpi buffer with adjustable feedback for romley platforms logic dif_in dif_in# hibw_bypm_lobw# smbdat smbclk ckpwrgd/pd# iref 7 smb_a0_tri smb_a1_tri 100m_133m# z-pll (ss compatible) dfb_out dfb_in dfb_in# oe(5_8,10_12)# dif(17:15, 13:10, 8:4, 2:0) output features ? 15 - 0.7v current mode differential hscl output pairs
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 2 pin configuration 64-pin mlf pll operating mode hibw_bypm_lobw# mode low pll lo bw mid bypass high pll hi bw note: pll is off in bypass mode tri-level input thresholds level voltage low <0.8v mid 1.2 2.2v power connections vdd gnd 63 64 analog pll 6 5 input circuit 19, 27, 41, 52, 60 24, 40, 55 dif clocks pin number description pll operating mode readback table hibw_bypm_lobw# byte0, bit 7 byte 0, bit 6 low (low bw) 0 0 mid (bypass) 0 1 high (high bw) 1 1 functionality at power up (pll mode) 100m_133m# dif_in ( mhz ) dif mhz 1 100.00 dif_in 0 133.33 dif_in smb_a1_tri smb_a0_tri 0 0 d8 0mda 0 1 de m0c2 m m c4 m 1 c6 1 0 ca 1 m cc 11ce 9zx21501 smbus addressin g pin smbus address (rd/wrt bit = 0) gnda vdda dif_17# dif_17 vdd dif_16# dif_16 dif_15# dif_15 gnd dif_13# dif_13 vdd oe12# dif_12# dif_12 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 iref 1 48 oe11# 100m_133m# 2 47 dif_11# hibw_bypm_lobw# 3 46 dif_11 ckpwrgd_pd# 4 45 oe10# gnd 5 44 dif_10# vddr 6 43 dif_10 dif_in 7 42 nc dif_in# 8 41 vdd smb_a0_tri 9 40 gnd smbdat 10 39 oe8# smbclk 11 38 dif_8# smb_a1_tri 12 37 dif_8 dfb_in 13 36 oe7# dfb_in# 14 35 dif_7# dfb_out# 15 34 dif_7 dfb_out 16 33 oe6# 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 dif_0 dif_0# vdd dif_1 dif_1# dif_2 dif_2# gnd dif_4 dif_4# vdd dif_5 dif_5# oe5# dif_6 dif_6# 9zx21501b
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 3 pin description pin # pin name type description 1 iref out this pin establishes the reference for the differential current-mode output pairs. it requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. other impedances require different values. see data sheet. 2 100m_133m# in 3.3v input to select operating frequency see functionality table for definition 3 hibw_bypm_lobw# in trilevel input to select high bw, bypass or low bw mode. see pll operatin g mode table for details. 4ckpwrgd_pd# in notifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. low enters power down mode. 5 gnd pwr ground pin. 6vddr pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 7 dif_in in 0.7 v differential true input 8 dif_in# in 0.7 v differential complementary input 9 smb_a0_tri in smbus address bit. this is a tri-level input that works in conjunction with the smb_a1 to decode 1 of 9 smbus addresses. 10 smbdat i/o data pin of smbus circuitry, 5v tolerant 11 smbclk in clock pin of smbus circuitry, 5v tolerant 12 smb_a1_tri in smbus address bit. this is a tri-level input that works in conjunction with the smb_a0 to decode 1 of 9 smbus addresses. 13 dfb_in in true half of differential feedback input, provides feedback signal to the pll for synchronization with the input clock to elimate phase error. 14 dfb_in# in complementary half of differential feedback input, provides feedback signal to the pll for synchronization with input clock to elimate phase error. 15 dfb_out# out complementary half of differential feedback output, provides feedback signal to the pll for synchronization with input clock to eliminate phase error. 16 dfb_out out true half of differential feedback output, provides feedback signal to the pll for synchronization with the input clock to eliminate phase error. 17 dif_0 out 0.7v differential true clock output 18 dif_0# out 0.7v differential complementary clock output 19 vdd pwr power supply, nominal 3.3v 20 dif_1 out 0.7v differential true clock output 21 dif_1# out 0.7v differential complementary clock output 22 dif_2 out 0.7v differential true clock output 23 dif_2# out 0.7v differential complementary clock output 24 gnd pwr ground pin. 25 dif_4 out 0.7v differential true clock output 26 dif_4# out 0.7v differential complementary clock output 27 vdd pwr power supply, nominal 3.3v 28 dif_5 out 0.7v differential true clock output 29 dif_5# out 0.7v differential complementary clock output 30 oe5# in active low input for enabling dif pair 5. 1 =disable outputs, 0 = enable outputs 31 dif_6 out 0.7v differential true clock output 32 dif_6# out 0.7v differential complementary clock output 33 oe6# in active low input for enabling dif pair 6. 1 =disable outputs, 0 = enable outputs 34 dif_7 out 0.7v differential true clock output 35 dif_7# out 0.7v differential complementary clock output 36 oe7# in active low input for enabling dif pair 7. 1 =disable outputs, 0 = enable outputs
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 4 pin description (continued) 37 dif_8 out 0.7v differential true clock output 38 dif_8# out 0.7v differential complementary clock output 39 oe8# in active low input for enabling dif pair 8. 1 = tri-state outputs, 0 = enable outputs 40 gnd pwr ground pin. 41 vdd pwr power supply, nominal 3.3v 42 nc n/a no connection. 43 dif_10 out 0.7v differential true clock output 44 dif_10# out 0.7v differential complementary clock output 45 oe10# in active low input for enabling dif pair 10. 1 = tri-state outputs, 0 = enable outputs 46 dif_11 out 0.7v differential true clock output 47 dif_11# out 0.7v differential complementary clock output 48 oe11# in active low input for enabling dif pair 11. 1 = tri-state outputs, 0 = enable outputs 49 dif_12 out 0.7v differential true clock output 50 dif_12# out 0.7v differential complementary clock output 51 oe12# in active low input for enabling dif pair 12. 1 = tri-state outputs, 0 = enable outputs 52 vdd pwr power supply, nominal 3.3v 53 dif_13 out 0.7v differential true clock output 54 dif_13# out 0.7v differential complementary clock output 55 gnd pwr ground pin. 56 dif_15 out 0.7v differential true clock output 57 dif_15# out 0.7v differential complementary clock output 58 dif_16 out 0.7v differential true clock output 59 dif_16# out 0.7v differential complementary clock output 60 vdd pwr power supply, nominal 3.3v 61 dif_17 out 0.7v differential true clock output 62 dif_17# out 0.7v differential complementary clock output 63 vdda pwr 3.3v power for the pll core. 64 gnda pwr ground pin for the pll core.
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 5 electrical characteristics - absolute maximum ratings parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - input/supply/common parameters ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ib yp v d d = 3.3 v, bypass mode 33 400 mhz 2 f i p ll v dd = 3.3 v, 100mhz pll mode 90 100.00 105 mhz 2 f i p ll v d d = 3.3 v, 133.33mhz pll mode 120 133.33 140 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c i ndif_i n dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1.8 ms 1,2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 cycles 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for the smbus to be active input current 3 time from deassertion until out p uts are >200 mv 4 dif_in input capacitance input frequency
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 6 electrical characteristics - clock input parameters ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (sin g le-ended measurement) 600 750 1150 mv 1 input low voltage - dif_in v ildif differential inputs (sin g le-ended measurement) v ss - 300 0 300 mv 1 input common mode volta g e - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentiall y 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j difin differential measurement 0 125 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero electrical characteristics - dif 0.7v current mode differential outputs ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes slew rate trf scope avera g in g on 1 2.5 4 v/ns 1, 2, 3 slew rate matchin g trf slew rate matchin g , scope avera g in g on 20 % 1, 2, 4 voltage high vhigh 660 750 850 1 voltage low vlow -150 150 1 max volta g evmax 1150 1 min voltage vmin -300 1 vswing vswing scope averaging off 300 mv 1, 2 crossin g volta g e (abs) vcross_abs scope avera g in g off 250 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset of v_cross_min/max (v_cros s absolute) allowed. the intent is to limit vcross induced modulation by settin g v_cross_delta to be smaller than v_cross absolute. mv statistical measurement on single-ended signal using oscillosc ope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? (100 ? differential impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and fa lling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling).
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 7 electrical characteristics - skew and differential jitter parameters ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode nominal value @ 25c, 3.3v -300 -200 -100 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode nominal value @ 25c, 3.3v 2.5 3.5 4.5 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll input-to-output skew varation in pll mode across voltage and temperature -50 0 50 ps 1,2,3,5,8 clk_in, dif[x:0] t dspo_byp input-to-output skew varation in bypass mode across voltage and temperature -250 250 ps 1,2,3,5,8 clk_in, dif[x:0] t dte random differential tracking error beween two 9zx devices in hi bw mode 35 ps (rms) 1,2,3,5,8 clk_in, dif[x:0] t dsste random differential spread spectrum tracking error beween two 9zx devices in hi bw mode 15 75 ps 1,2,3,5,8 dif{x:0] t skew_all output-to-output skew across all outputs (common to bypass and pll mode) 45 65 ps 1,2,3,8 pll jitter peaking j p eak-hib w lobw#_bypass_hibw = 1 0 1 2.5 db 7,8 pll jitter peaking j p eak-lob w lobw#_bypass_hibw = 0 0 1 2 db 7,8 pll bandwidth pll hi bw lobw#_bypass_hibw = 1 2 3 4 mhz 8,9 pll bandwidth pll lobw lobw#_bypass_hibw = 0 0.7 1 1.4 mhz 8,9 duty cycle t dc measured differentially, pll mode 45 50 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 0 2 % 1,10 pll mode 24 50 ps 1,11 additive jitter in bypass mode 20 50 ps 1,11 notes for preceding table: 6. t is the period of the input clock 7 measured as maximum pass band gain. at frequencies within the loop bw, highest point of magnification is called pll jitter pe aking. 8. guaranteed by design and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 10 duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. 11 measured from differential waveform 3 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4 this p arameter is deterministic for a g iven device 5 measured with scope averaging on to find mean value. dif_in slew rate must be matched to dif output slew rate. jitter, cycle to cycle t jcyc-cyc 1 measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding inp ut. 2 measured from differential cross- p oint to differential cross- p oint. this p arameter can be tuned with external feedback p ath, if p resent.
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 8 power management table outputs ckpwrgd?/pd# dif_in/ dif_in# smbus en bit oe# pin dif(5:8,10:12)/ dif(5:8,10:12)# other dif/ dif# dfb_out/ dfb_out# 0xxx hi-z 1 hi-z 1 hi-z 1 off 0x hi-z 1 hi-z 1 running on 1 0 running running running on 11 hi-z 1 running runnin g on note: 1. due to external pull down resistors, hi-z results in low/low on the true/complement outputs running control bits/pins pll state inputs 1 electrical characteristics - phase jitter parameters ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes t jp hpcieg1 pcie gen 1 36 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.2 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1.9 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.5 1 ps (rms) 1,2,4 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.31 0.5 ps (rms) 1,5 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.21 0.3 ps (rms) 1,5 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.17 0.2 ps (rms) 1,5 t jp hpcieg1 pcie gen 1 4 10 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.25 0.3 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.57 0.7 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.20 0.3 ps (rms) 1,2,4,6 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.22 0.3 ps (rms) 1,5,6 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.08 0.1 ps (rms) 1,5,6 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.08 0.1 ps (rms) 1,5,6 1 applies to all outputs. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total jittter)^2 - (i nput jitter)^2 4 sub j ect to final radification b y pci sig. 5 calculated from intel-su pp lied clock jitter tool v 1.6.3 t jphpcieg2 t jphqpi_smi 2 see htt p ://www. p cisi g .com for com p lete s p ecs 3 sam p le size of at least 100k c y cles. this fi g ures extra p olates to 108 p s p k- p k @ 1m c y cles for a ber of 1-12. additive phase jitter, bypass mode jitter, phase t jphpcieg2 t jphqpi_smi electrical characteristics - current consumption ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes operating supply current i dd3. 3op all outputs active @100mhz, c l = full load; 390 425 ma 1 powerdown current i dd3. 3pdz all differential pairs tri-stated 5 15 ma 1 1 guaranteed by design and characterization, not 100% tested in production.
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 9 clock periods - differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4 dif measurement windo w units notes ssc off center freq. mhz clock periods - differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4 notes: 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, 100 mhz pll mode or bypass mode 4 driven b y cpu output of main clock, 133 mhz pll mode or b y pass mode 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck420bq/ck410b+ accuracy requirements (+/-100ppm). the 9zx21501 itself does not contribute to ppm error. dif notes measurement windo w units ssc on center freq. mhz differential output termination table dif zo ( ? )iref ( ? )rs ( ? )rp ( ? ) 100 475 33 50 85 412 27 43.2 differential zo rp rp hscl output buffer 9zx21501 differential test loads rs rs 2pf 2pf
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 10 general smbus serial interface information for the 9zx21501b how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address xx (h) ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the data byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? idt clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address xx (h) ? idt clock will acknowledge ? controller (host) sends the begining byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read addressyy (h) ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n + x -1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit idt (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address xx ( h ) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit idt ( slave/receiver ) controller (host) x byte ack ack data byte count = x ack slave address yy ( h ) index block read operation slave address xx ( h ) beginning byte = n ack ack note: xx (h) is defined by smbus address select pins.
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 11 smbustable: pll mode, and frequency select register pin # name control function t yp e0 1 default bit 7 pll mode 1 pll o p eratin g mode rd back 1 r latch bit 6 pll mode 0 pll o p eratin g mode rd back 0 r latch bit 5 1 bit 4 dif_17_en out p ut control overrides oe# p in rw hi-z enable 1 bit 3 dif_16_en out p ut control overrides oe# p in rw hi-z enable 1 bit 2 0 bit 1 0 bit 0 100m_133# fre q uenc y select readback r 133mhz 100mhz latch smbustable: output control register pin # name control function t yp e0 1 default bit 7 dif_7_en out p ut control overrides oe# p in rw 1 bit 6 dif_6_en out p ut control overrides oe# p in rw 1 bit 5 dif_5_en out p ut control overrides oe# p in rw 1 bit 4 dif_4_en out p ut control overrides oe# p in rw 1 bit 3 1 bit 2 dif_2_en out p ut control overrides oe# p in rw 1 bit 1 dif_1_en out p ut control overrides oe# p in rw 1 bit 0 dif_0_en out p ut control overrides oe# p in rw 1 smbustable: output control register pin # name control function t yp e0 1 default bit 7 dif_15_en out p ut control overrides oe# p in rw hi-z enable 1 bit 6 1 bit 5 dif_13_en out p ut control overrides oe# p in rw 1 bit 4 dif_12_en output control overrides oe# pin rw 1 bit 3 dif_11_en out p ut control overrides oe# p in rw 1 bit 2 dif_10_en out p ut control overrides oe# p in rw 1 bit 1 1 bit 0 dif_8_en out p ut control overrides oe# p in rw hi-z enable 1 smbustable: output enable pin status readback register pin # name control function t yp e0 1 default bit 7 oe_rb12 real time readback of oe#12 r real time bit 6 oe_rb11 real time readback of oe#11 r real time bit 5 oe_rb10 real time readback of oe#10 r real time bit 4 0 bit 3 oe_rb8 real time readback of oe#8 r real time bit 2 oe_rb7 real time readback of oe#7 r real time bit 1 oe_rb6 real time readback of oe#6 r real time bit 0 oe_rb5 real time readback of oe#5 r real time smbustable: reserved register pin # name control function t yp e0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 oe# pin low oe# pin high reserved reserved reserved reserved hi-z enable hi-z enable see pll operating mode readback table reserved 39 31/32 28/29 25/26 53/54 b y te 3 37/38 48 51 45 22/23 20/21 17/18 56/57 43/44 b y te 2 b y te 0 3 3 49/50 61/62 58/59 2 b y te 1 34/35 46/47 36 b y te 4 33 30 reserved reserved oe# pin low oe# pin high hi-z enable reserved reserved reserved reserved reserved reserved reserved reserved
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 12 smbustable: vendor & revision id register pin # name control function t yp e0 1 default bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function t yp e0 1 default bit 7 r1 bit 6 r1 bit 5 r0 bit 4 r1 bit 3 r1 bit 2 r0 bit 1 r1 bit 0 r1 smbustable: byte count register pin # name control function t yp e0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 smbustable: reserved register pin # name control function t yp e0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 vendor id device id 2 device id 1 device id 4 revision id b rev = 0001 c rev = 0010 - - b y te 8 - - - - - - reserved - device id 3 - writing to this register configures how many bytes will be read back. device id 0 default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. - reserved reserved reserved reserved reserved reserved b y te 7 - - - - - - - b y te 5 - b y te 6 - - reserved reserved reserved device id is 219 decimal or db hex. device id 7 (msb) reserved device id 5 device id 6
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 13 common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 dif reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 14 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt ? 15-output differential zbuffer for pcie gen2/3 and qpi 1629c - 12/15/11 9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 15 e top view or anvil singulation a3 l n (ref.) e e e e (ref. ) (ref. ) (ref. ) (typ.) if a1 even e2 d2 d2 2 a c 0.08 c e2 2 2 2 1 sawn singulation index area seating plane are even thermal base odd b (n - 1)x n 1 chamfer 4x 0.6 x 0.6 max optional d d & & n d n d n e n e & n d n e (n - 1)x e dimensions dimensions (mm) symbol min. max. a0.81.0 n64 a1 00.05 n d 16 a3 n e 16 b 0.18 0.3 e d x e basic d2 min. / max. 6.00 6.25 e2 min. / max. 6.00 6.25 l min. / max. 0.30 0.50 thermally enhanced, very thin, fine pitch quad flat / no lead plastic package symbol 64l 0.25 reference 0.50 basic 9.00 x 9.00 ordering information part / order number shipping package package temperature 9zx21501bklf trays 64-pin mlf 0 to +70c 9ZX21501BKLFT tape and reel 64-pin mlf 0 to +70c "lf" designates pb-free configuration, rohs compliant. "b" is the device revision designator (will not correlate with the datasheet revision).
9zx21501b 15-output differential zbuffer for pcie gen2/3 and qpi 16 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issue date who description page # 0.1 2/17/2010 rdw initial release - 0.2 5/5/2010 rdw 1. updated pin 6 name to vddr to indicate that this pin should be decoupled as analog pin 2. added missing pin 37 to the pin description table on page 4 of ds 1, 4 0.3 8/2/2010 rdw 1. correction to key specifications bullets 2. updated electrical tables to new 9zx2 standard, added termination table and figure 3. added note about smbus addresses to page 10, changed ics to idt 4. updated revision id to indicate rev b and rev c. 5. corrected minor typos. 6. added additive p hase j itter table for b yp ass mode. 1-3, 5- 11,13 a 8/5/2010 rdw move to final. b 12/8/2011 rdw 1. updated tdspo_byp parameter from +/-350 to +/-250ps 7 c 12/15/2011 rdw 1. lowered idd3.3op from max 500ma/typ 407ma to max 425ma/ typ 390ma 2. lowered idd3.3pdz from max36ma/typ 12ma to max 15ma/ typ 5ma 8

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